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[VHDL-FPGA-Verilog] deinterlace

Description: Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
Platform: | Size: 99328 | Author: cloud | Hits:

[VHDL-FPGA-Verilog] aes_core.tar

Description: AES的Verilog实现,用于加密的算法硬件实现!-AES realize the Verilog for hardware implementation of encryption algorithms!
Platform: | Size: 69632 | Author: 刘志刚 | Hits:

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